CT32B0=DISABLED, ROM=DISABLED, SSP1=DISABLE, SSP=DISABLED, CT32B1=DISABLED, I2C=DISABLED, USB_REG=DISABLED, FLASHREG=DISABLED, ADC=DISABLED, WDT=DISABLED, IOCON=DISABLED, SYS=RESERVED, RAM=DISABLED, UART=DISABLED, GPIO=DISABLED, FLASHARRAY=DISABLED, CT16B0=DISABLED, CT16B1=DISABLED
System AHB clock control
| SYS | Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M3 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. 0 (RESERVED): Reserved 1 (ENABLED): Enabled |
| ROM | Enables clock for ROM. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| RAM | Enables clock for RAM. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| FLASHREG | Enables clock for flash register interface. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| FLASHARRAY | Enables clock for flash array access. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| I2C | Enables clock for I2C. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| GPIO | Enables clock for GPIO. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| CT16B0 | Enables clock for 16-bit counter/timer 0. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| CT16B1 | Enables clock for 16-bit counter/timer 1. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| CT32B0 | Enables clock for 32-bit counter/timer 0. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| CT32B1 | Enables clock for 32-bit counter/timer 1. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| SSP | Enables clock for SSP. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| UART | Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| ADC | Enables clock for ADC. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| USB_REG | Enables clock for USB_REG. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| WDT | Enables clock for WDT. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| IOCON | Enables clock for IO configuration block. 0 (DISABLED): Disabled 1 (ENABLED): Enabled |
| RESERVED | Reserved |
| SSP1 | Enables clock for SPISP1. 0 (DISABLE): Disable 1 (ENABLE): Enable |
| RESERVED | Reserved |